1. Technical Field
The present invention relates in general to logic signal switching devices, and in particular, to bipolar/BiCMOS logic circuits for high speed low power switching of a signal between a first prescribed state and a second prescribed state. Signal switching is accomplished pursuant to the invention using an active signal pull-up circuit in combination with a self-biased, feedback-controlled active signal pull-down circuit.
2. Background Art
In bipolar/BiCMOS digital circuits such as emitter-coupled logic (ECL), non-threshold logic (NTL), and memory circuits, a circuit output stage typically includes pull-up and pull-down signal switching circuits connected in tandem. This tandem connection of circuits is designed to drive a load to a "1" output logic level or to a "0" output logic level based on the output state of an associated logic circuit. Output level switching circuits ideally operate at high speed to establish a corresponding logic "1" or a logic "0" condition for a subsequent semiconductor circuit. Traditional implementations of logic switching circuits with signal pull-up and pull-down functions, typically implement signal pull-up much more rapidly than the pull-down function.
For example, one widely used implementation of a pull-down circuit consists of a resistor, or other current-source pull-down structure, in combination with a standard emitter follower signal pull-up stage to drive the output. Such a signal pull-down approach is referred to as passive pull-down and its primary advantages are simplicity and versatility (e.g., collector-dotting and emitter-dotting are both possible). Unfortunately, a passive pull-down approach fails in contemporary large scale integration implementations where circuits must function at high speed with little power consumption. A principal reason for this is that as consumed power is reduced by minimizing pull-down circuit current, the pull-down switching delay time increases reciprocally, a result obviously counter to high speed signal switching.
As a solution, various active signal pull-down circuits are available for low-power high-speed applications. One particularly popular technique is to set the steady state pull-down current through the inclusion of extra bias circuitry and the utilization of ac (or capacitive) coupling to actively modulate the current in a push-pull manner during input signal transition periods. Pull-down speed is improved by providing a large momentary sink current, while minimizing dc power consumption by setting the steady state current low. Besides the problematic introduction of power supply noise via transient current and circuit complexity, this active pull-down approach restricts the use of emitter-dotting configurations, especially for dc-coupled or complementary push-pull emitter follower circuits. For such circuits, emitter-dotting is simply impractical.
Existing active pull-down emitter follower circuits generally require the addition of an out of phase (complementary) signal for push-pull control. This produces another restriction in that collector-dotting (and even cascoding in some cases) is not allowed, and delay in the preceding logic stage increases through the addition of loading on the out-of-phase signal node. Also, because the push-pull action is input signal driven, transient pull-down current could remain unnecessarily high or low after the output has finished a transition, or could return to a steady state value prematurely before the output circuits complete the transition.
Therefore, a need exists in large scale bipolar/BiCMOS/CMOS logic circuit technology for a signal switching circuit stage having improved performance characteristics over presently available signal switching circuits employing a passive or previously available active signal pull-down approach.